Test bus interfaces exist which allow serial data to be shifted in and out of integrated circuits to facilitate testing of the logic in the device. These buses are designed primarily to transfer a single pattern of serial data into and out of a selected scan path surrounding the circuit under test once per shift operation. Depending on the complexity of the circuit, potentially thousands or hundreds of thousands of shift operations may be required to fully test the circuit. Having to repeat a shift operation multiple times to transfer test data patterns into and out of the circuit being tested is time consuming.
IEEE 1149.1 Test Bus and Architecture Description
While many types of test buses exist, the IEEE 1149.1 test bus will be used in this disclosure to describe the advantages of the invention. The IEEE standard IC test bus and architecture described in the 1149.1 specification is shown in FIG. 1. This architecture has been developed to provide a standard method to serially access serial test registers in IC designs to facilitate testing. This test architecture, shown in FIG. 1, consists of an instruction register (IREG), a set of data registers (DREG) referred to as Bypass, DREG1, and DREG2, and a test interface referred to as a Test Access Port (TAP). While only one IREG may be implemented in the architecture, any number of DREGs can be included. Each DREG of FIG. 1 is associated with the input and output boundary of a circuit in the IC to enable serial testing of the circuit. The Bypass DREG is not used for testing, but rather for providing an abbreviated scan path through the IC when testing of circuits, associated with DREG1 and DREG2, is not required.
The IREG and DREGs exist on separate scan paths arranged in parallel between the test data input pin (TDI) 102 and test data output pin (TDO) 116. During IREG scan operations the TAP receives external control via the test mode select (TMS) 104 and test clock (TCK) 106 and outputs internal control via the control bus 108 to shift data through the IREG from the TDI input to the TDO output. Similarly, DREG scan operations are accomplished by the TAP receiving external control on the TMS and TCK input and outputting internal control on control bus 108 to shift data through the selected DREGs. Control for selecting one of the DREGs comes from the instruction shifted into the IREG and is output from the IREG via control bus 110. The control output on bus 110 is input to all DREGs and selects one for shifting. Control bus 110 is also input to multiplexer 1 to couple the serial output of the selected DREG to the TDO output.
The TAP is a finite state machine which responds to a scan access protocol input via the TMS and TCK inputs. The purpose of the TAP is to respond to the input scan access protocol to shift data through either the IREG or DREG. The TAP is clocked by the TCK input and makes state transitions based on the TMS input. The TAP state diagram is shown in FIG. 2 and consists of sixteen states: test logic reset (TLRESET), run test/idle (RT/IDLE), select data register scan (SELDRS), select instruction register scan (SELIRS), capture data register (CAPTUREDR), shift data register (SHIFTDR), exit1 data register (EXITDRr), pause data register scan (PAUSEDR), exit2 data register (EXIT2DR), update data register (UPDATEDR), capture instruction register (CAPTUREIR), shift instruction register (SHIFTIR), exit1 instruction register (EXIT1IR), pause instruction register Scan (PAUSEIR), exit2 instruction register (EXIT2IR), and update instruction register (UPDATEIR).
At power up or during normal operation of the host IC, the TAP will be in the TLRESET state. In this state, the TAP issues a reset signal that places all test logic in a condition that will not impede normal operation of the host IC. When test access is required, a protocol is applied via the TMS and TCK inputs, causing the TAP to exit the TLRESET state and enter the RT/IDLE state. In
FIG. 2, the TMS input that causes movements between the TAP states is indicated by a logic 0 or 1. TCK is the clock that causes the TAP state controller to transition from state to state.
From the RT/IDLE state, an instruction register scan protocol can be issued to transition the TAP through the SELDRS and SELIRS states to enter the CAPTUREIR state. The CAPTUREIR state is used to preload the IREG with status data to be shifted out of the TDO output pin. From the CAPTUREIR state, the TAP transitions to either the SHIFTIR or EXIT1IR state. Normally the SHIFTIR will follow the CAPTUREIR state so that the preloaded data can be shifted out of the IREG for inspection via the TDO output while new data is shifted into the IREG via the TDI input. Following the SHIFTIR state, the TAP either returns to the RT/IDLE state via the EXIT1IR and UPDATEIR states or enters the PAUSEIR state via EXIT1IR. The reason for entering the PAUSEIR state would be to temporarily suspend the shifting of data through the IREG. From the PAUSEIR state, shifting can be resumed by re-entering the SHIFTIR state via the EXIT2IR state or it can be terminated by entering the RT/IDLE state via the EXIT2IR and UPDATEIR states.
From the RT/IDLE state, a data register scan protocol can be issued to transition the TAP through the SELDRS state to enter the CAPTUREDR state. The CAPTUREDR state is used to preload the selected DREG with data to be shifted out of the TDO output pin. From the CAPTUREDR state, the TAP transitions to either the SHIFTDR or EXIT1DR state. Normally the SHIFTDR will follow the CAPTUREDR state so that the preloaded data can be shifted out of the DREG for inspection via the TDO output while new data is shifted into the DREG via the TDI input. Following the SHIFTDR state, the TAP either returns to the RT/IDLE state via the EXIT1DR and UPDATEDR states or enters the PAUSEDR state via EXIT1DR. The reason for entering the PAUSEDR state would be to temporarily suspend the shifting of data through the DREG. From the PAUSEDR state, shifting can be resumed by re-entering the SHIFTDR state via the EXIT2DR state or it can be terminated by entering the RT/IDLE state via the EXIT2DR and UPDATEDR states.
In application, any number of ICs that implement the IEEE 1149.1 architecture can be serially connected together at the circuit board level as shown in FIG. 3. Similarly, any number of circuit boards can be connected together to further increase the number of ICs serially connected together. The ICs in FIG. 3 are connected serially via their TDI input and TDO output pins from the first to the last IC. Also each IC receives TMS and TCK control inputs from a test bus controller. The test bus controller also outputs serial data to the TDI input of the first IC in the serial path and receives serial data from the TDO of the last IC in the serial path. The test bus controller can issue control on the TMS and TCK signals to cause all the ICs to operate together to shift data through either their internal IREG or DREGs, according to the TAP protocol procedure previously described.
During IREG shift operations the total length of the shift path is equal to the sum of the bits in each ICs IREG. For example, if one hundred ICs are in the serial path (FIG. 3) and each ICs IREG is 8 bits long, the number of bits that must be shifted per IREG shift operation is eight hundred. Similarly, during DREG shift operations the total length of the serial path is equal to the sum of the bits in each ICs selected DREG. If the Bypass DREG is selected in each IC the total number of bits shifted during a DREG scan is equal to the number of ICs times 1 bit, since the Bypass DREG is only one bit long. Each IC can select a different DREG by loading in different instructions into the IREG. For instance the first IC could be selecting a DREG with many bits while all other select their Bypass DREG. Typically when no testing is being performed in an IC its Bypass DREG is selected to reduce the ICs DREG bit length to a single bit.
The following example describes how a combinational circuit associated with an IC's DREG can be tested using 1149.1 TAP data register scan operations in a single IC test environment consisting of an IC to be tested and connections to a test bus controller (FIG. 4). This type of testing would be done by the IC vendor to verify the IC. The IC contains a DREG that is coupled to the boundary of a combinational circuit to allow the test bus controller to input and output test patterns to the circuit via the serial test bus.
FIG. 5 shows a detailed view of DREG1 of the target IC of FIG. 4 coupled to the input and output boundary of a combinational circuit. The combinational circuit could be a subcircuit within an IC or an entire IC. A combinational circuit consists of boolean logic functions with no memory or register storage. Examples of combinational circuits include but are not limited too; boolean logic blocks, address decoders, programmable logic arrays, comparators, multiplexers, and arithmetic logic units. The output response of a combinational circuit is a function of only the input stimulus. DREG1 is shown having two parts, a data input shift register (DISR) and a data output shift register (DOSR).
The DISR consists of a series of scan cells (I) and receives serial test data input from TDI and control input from the TAP. The DISR outputs serial data to the DOSR and parallel data to the combinational circuit inputs. The DOSR consists of a series of scan cells (O) and receives serial test data input from the DISR and parallel input from the combinational circuit. The DOSR outputs serial data to the TDO output. The TAP receives control input from the test bus controller via the TMS and. TCK inputs and outputs control to the DISR and DOSR. The combinational circuit receives parallel test data from the DISR and outputs parallel data to the DOSR.
The DISR and DOSR may either be dedicated test logic or functional logic associated with the combinational circuit that is modifiable during test to operate as test logic. During test the scan cells of the DISR respond to control input from the TAP to input and output serial data and to output parallel data to the combinational circuit. When the TAP is inputting control to shift data through the DISR, the parallel outputs are held at the previous parallel output state. When the shift operation is complete the TAP inputs control to allow the parallel outputs to be updated with the new parallel output state that has been shifted into the DISR. Also during test, the scan cells of the DOSR respond to control input from the TAP to capture the parallel data output from the combinational circuit and then shift the captured data out the serial output of the DISR and IC to the test bus controller via the TDO output.
Prior to testing, the test bus controller inputs a test command into the IC's instruction register that selects DREG1 and the combinational circuit for testing. In this configuration, the total scan path length seen by the test bus controller is the bits in the DISR (I) plus the bits in the DOSR (O).
After loading the test command the test bus controller inputs control to cause the TAP to execute multiple data register scan operations. The data register scan operation is described in the TAP state diagram of FIG. 2. A single data register scan operations involves transition through the following states; SELDRS to CAPTUREDR to SHIFTDR to EXIT1DR to UPDATEDR.
Each data register scan operation repeats the steps of (1) capturing parallel data from the combinational circuit into the DOSR of the IC, (2) shifting data through the DISR and DOSR of the IC to output the captured data and input new test data, and (3) updating and parallel outputting the new test data from the DISR to the combinational circuit. Steps 1 and 3 (capturing and updating) require one TCK bus cycle each. Step 2 (shifting) requires a number of TCK bus cycles equal to the number of scan cells in the DISR (I) and DOSR (O).
Equation 1 represents the number of TCK bus cycles required per data register scan operation, equation 2 represents the number of data register scan operations required to completely test the combinational circuit, and equation 3 represents the required test time. For the sake of simplifying the examples, the other intermediate states the TAP transitions through during data register scan operations are not used in the equations (i.e. SELDRS and EXIT1DR).
                              #          ⁢                                          ⁢          of          ⁢                                          ⁢                                    TCK              s                        /            scan                    ⁢                                          ⁢          operation                =                                            (              CaptureDR              )                        +                          (              ShiftDR              )                        +                          (              UpdateDR              )                                =                                    (              1              )                        +                          (                              I                +                O                            )                        +                          (              1              )                                                          Eq1        .                            Where: I=the # of DISR bits        O=the # of DOSR bits# of Scan Operations=2I (I=the # of combinational data inputs)  Eq2.Test Time=(Eq1)×(Eq2)×(1/TCKfreq)  Eq3.        
To establish a test time calculation benchmark for the single IC test environment using multiple 1149.1 data register scan operations, assume that; I=16, O=16, and the TCK frequency=10 Mhz. The calculated test time to test the combinational circuit is:Test time=(1+16+16+1)×(216)=( 1/10 Mhz)=222.8 ms  Eq3
While the calculated test time benchmarks for the combinational circuit may seem like insignificant amount of time, the circuit being tested may be one of a hundred similar circuits in the IC that need to be tested via the 1149.1 TAP to completely test the IC. Testing 100 combinational circuits would take 100×222.8 ms or 22.28 seconds. This test time is extremely long for an IC manufacturing test.
The following example describes how a sequential circuit associated with an IC's DREG can be tested using 1149.1 TAP data register scan operations in a single IC test environment consisting of an IC to be tested and connections to a test bus controller (FIG. 4). This type of testing would be done by the IC vendor to verify the IC. The IC contains a DREG that is coupled to the boundary of a sequential circuit to allow the test bus controller to input and output test patterns to the circuit via the serial test bus.
FIG. 6 illustrates a detailed view of DREG1 of the target IC of FIG. 4 coupled to the input and output boundary of a sequential circuit. The sequential circuit could be a subcircuit within an IC or an entire IC. A sequential circuit includes boolean logic functions combined with memory or register storage. Examples of sequential circuits include but are not limited to: read/write memories, fifo memories, counters, state machines, microprocessors, and microcomputers. The output response of a sequential circuit is a function of input stimulus, stored internal control or states, and clock or control inputs. DREG1 is shown having three parts; a data input shift register (DISR), a control input shift register (CISR), and a data output shift register (DOSR).
The DISR consists of a series of scan cells (I) and receives serial test data input from TDI and control input from the TAP. The DISR outputs serial data to the CISR and parallel data to the sequential circuit inputs. The CISR consists of at least one scan cell (C) and receives serial test data input from the DISR and control input from the TAP. The CISR outputs serial data to the DOSR and control to the sequential circuit. The DOSR consists of a series of scan cells (O) and receives serial test data input from the CISR and parallel input from the sequential circuit. The DOSR outputs serial data to the TDO output. The TAP receives control input from a test bus controller via the TMS and TCK inputs and outputs control to the DISR, CISR, and DOSR. The sequential circuit receives parallel test data input from the DISR and control input from the CISR and outputs parallel data to the DOSR.
The DISR, CISR, and DOSR may either be dedicated test logic or functional logic associated with the sequential circuit that is modifiable during test to operate as test logic. During test the scan cells of the DISR and CISR respond to control input from the TAP to input serial data from the TDI input pin and to output parallel data and control to the sequential circuit. When the TAP is inputting control to shift data into the DISR and CISR, their parallel outputs are held at the previous parallel output state. When the shift operation is complete the TAP inputs control to allow the parallel outputs to be updated with the new parallel output state that has been shifted into the DISR and CISR. Also during test the scan cells of the DOSR respond to control input from the TAP to capture the parallel data output from the sequential circuit and then shift the captured data out the serial output of the DOSR and IC via TDO.
During test, the test bus controller inputs control via the TAP to execute a data register scan operation as described in the TAP state diagram of FIG. 2. Each data register scan operation repeats the steps of (1) capturing parallel data from the sequential circuit into the DOSR during the CaptureDR state, (2) shifting new test input data into the DISR and CISR and captured output test data from the DOSR during the ShiftDR state, and (3) updating and inputting the new parallel test data and control from the DISR and CISR to the sequential circuit during the UpdateDR state.
Step 1 (capturing) and step 3 (inputting) require one TCK bus cycle each. Step 2 (shifting) requires a number of TCK bus cycles equal to the number of scan cells in the DISR (I), CISR (C), and DOSR (O). For the sake of simplifying the description, the other intermediate states the TAP must transition through during data register scan operations are not included.
Testing of the sequential circuit differs from the combinational circuit in that additional data register scan operations are required to activate the CISR control input to the sequential circuit, to allow the sequential circuit to respond to the parallel data inputs from the DISR and output parallel data to the DOSR. Each activation of a control input to the sequential circuit requires one data register scan operation to enable the control input, and another data register scan operation to disable the control input. Thus each activation required by the sequential circuit requires a pair of data register scan operations. In addition, the data register scan operations to enable and disable the control input follows the data register scan that inputs the data pattern to the sequential circuit. So the total number of data register scan operations required to apply a single test pattern to a sequential circuit is equal to; an initial data register scan operation to input the data pattern, plus a pair of data register scan operations for each time a control input needs to be activated, i.e. enabled and disabled.
For example, for one control input activated twice per applied test data pattern, five data register scan operations are required. A first scan operation inputs the data pattern to the sequential circuit, a second scan operation re-enters the data pattern and enables the control input to start the first activation, a third scan operation re-enters the data pattern and disables the control input to stop the first activation, a fourth scan operation re-enters the data pattern and enables the control input to start the second activation, and a fifth scan operation re-enters the data pattern and disables the control input to stop the second activation. A sixth scan operation enters the next data pattern to start the next control activation sequence and outputs the response of the sequential circuit to the previous data pattern.
Equation 4 represents the number of TCK bus cycles required per data register scan operation, equation 5 represents the number of data register scan operations required to completely test the sequential circuit, and equation 6 represents the required test time.
                              #          ⁢                                          ⁢          of          ⁢                                          ⁢                      TCKs            /            scan                    ⁢                                          ⁢          operation                =                                            (              CaptureDR              )                        +                          (              ShiftDR              )                        +                          (              UpdateDR              )                                =                      (                          1              +              I              +              C              +              O              +              1                        )                                              Eq4        .            
Where: I=the # of DISR bits                C=the # of CISR bits        O=the H of DOSR bits# of Scan Operations=2I×(1+2K)  Eq5.        
Where: I=the # of data inputs                K=the # of control input activationsTest Time=(Eq4)×(Eq5)×(1/TCKfreq)  Eq6.        
To establish a test time calculation benchmark for a sequential circuit using multiple 1149.1 TAP data register scan operations, assume that; I=16, C=1, K=3, O=16, and TCK frequency=10 Mhz. The calculated test time is;Test Time=(1+16+1+16+1)×(216×7)×( 1/10 Mhz)=1.60s  Eq6
While the calculated test time benchmarks for the sequential circuit may seem like insignificant amounts of time, the circuit being tested may be one of a hundred similar circuits in the IC that need to be tested via the 1149.1 TAP to completely test the IC. Testing 100 sequential circuits (with C=1 and K=3) would take 100×1.60 s or 160 seconds. This test time is extremely long for an IC manufacturing test.
To illustrate the effect that multiple control input activations have on the 1149.1 test time of sequential circuits, Eq6 is repeated for control input activations of K=1, 2, 4, and 5 under the same test conditions listed above.Test Time (K=1)=(2+16+1+16)×(216×3)×( 1/10 Mhz)=688.13 ms  Eq6Test Time (K=2)=(2+16+1+16)×(216×5)×( 1/10 Mhz)=1.15 seconds  Eq6Test Time (K=4)=(2+16+1+16)×(2×9)×( 1/10 Mhz)=2.06 seconds  Eq6Test Time (K=5) (2+16+1+16)×(216×11)×( 1/10 Mhz)=2.52 seconds  Eq6
From the above repeated calculations of Eq 6 it is seen that testing 100 sequential circuits with K=1 takes 68.81 seconds, with K=2 takes 115 seconds, with K=4 takes 206 seconds, and with K=5 takes 252 seconds. To make the situation worse, some sequential circuits such as microprocessors and micro-controllers have multiple control inputs that must be activated individually and multiple times in order for the sequential circuit to react to an input pattern, execute its internal microcode, and output a response pattern. The lengthy test times required for testing these more complex sequential circuits via 1149.1 force them to be tested by other means or not at all.
The following example describes how a combinational circuit associated with an IC's DREG can be tested using 1149.1 TAP data register scan operations in a multiple IC environment shown in FIG. 7. The combinational circuit could be a subcircuit in the IC or the entire IC. This type of testing would be done at a higher assembly level where the IC is combined with other ICs to form a system. The system could be anything from a simple electronic toy to complex electronics used in military aircraft. The middle IC of FIG. 7, referred to as the target (T), in the group contains the DREG1 and the combinational circuit of FIG. 5. There are “N” ICs between the target IC's TDI input and the test bus controller's TDO output and “M” IC's between the target ICs TDO and the test bus controller's TDI input.
During test the DISR and DOSR of FIG. 5 operate as described in the test of the combinational circuit in the single IC environment. The only difference between the multiple and single IC test environment is the length of the scan path between the test bus controller and the target IC.
Prior to testing, the test bus controller inputs test commands into the ICs of FIG. 7. ICs 1-N and ICs 1-M are loaded with a Bypass instruction to select their Bypass DREGs, and the target IC (T) is loaded with a test instruction that selects DREG1 and the combinational circuit for testing. In this configuration, the scan path length seen by the test bus controller is N bits (one bit for each IC 1-N), plus the target ICs DREG1 bits, plus M bits (one bit for each IC 1-M).
After loading the test commands the test bus controller inputs control to cause the TAP of each IC to execute multiple data resister scan operations. Each data register scan operation repeats the steps of (1) capturing parallel data into the selected DREG of each IC in the scan path, (2) shifting data through the selected DREG of each IC in the scan path to output the captured data and input new test data, and (3) updating to parallel output the new test data from the selected DREG of each IC in the scan path. Steps 1 and 3 (capturing and updating) require one TCK bus cycle each. Step 2 (shifting) requires a number of TCK bus cycles equal to the number of scan cells in the DISR (I) and DOSR (O), plus the number of scan cells in the Bypass DREG of ICs 1-N and 1-M of FIG. 7.
It is important to note that step 1 (parallel capture operation) causes the current data in the DREGs to be overwritten with the data captured. In the multiple IC environment this means that each time an 1149.1 data register scan operation is repeated, the new data to be shifted into the DISR and applied to the combinational circuit must traverse the entire length of Bypass DREGs of ICs 1-N between the test bus controller's TDO output and the target ICs TDI input. Likewise, the data captured in the DOSR of the target IC must traverse the entire length of the Bypass DREGs of ICs 1-M between the target IC's TDO output and the test bus controller's TDI input. The Bypass DREGs of ICs 1-N and 1-M cannot be used to store or pipeline test data between the test bus controller and the target IC.
Equation 7 represents the number of TCK bus cycles required per data register scan operation, equation 2 represents the number of data register scan operations required to completely test the combinational circuit, and equation 8 represents the required test time.
                              #          ⁢                                          ⁢          of          ⁢                                          ⁢                                    TCK              s                        /            scan                    ⁢                                          ⁢          operation                =                                            (              CaptureDR              )                        +                          (              ShiftDR              )                        +                          (              UpdateDR              )                                =                      (                          1              +              N              +              I              +              O              +              M              +              1                        )                                              Eq7        .                            Where: N=the # of bits before the target IC                    I=the # of DISR bits            O=the # of DOSR bits            M=the # of bits after the target IC# of Scan Operations=2I (I=the # of combinational data inputs)  Eq2Test Time=(Eq7)×(Eq2)×(1/TCKfreq)  Eq8.                        
To establish a test time calculation benchmark for the multiple IC test environment using multiple 1149.1 TAP data register scan operations to test combinational circuits, assume that; N=500, I=16, O=16, M=500, and the TCK frequency=10 Mhz. The calculated test time to test the combinational circuit is:Test Time=(1+500+16+16+500+1)×(216)×( 1/10 Mhz)=6.78 seconds.  Eq8
As in the single IC test environment, the complete testing of the IC in a multiple IC environment may require repeating the test on 100 other combinational circuits. In addition, the system may contain 1000 additional ICs of similar complexity as the one tested. Testing 100 combinational circuits in an IC would take 100×6.78 seconds or 678 seconds or 11.3 minutes. Testing 1000 ICs of similar complexity would take 11,300 minutes or 188 hours or 7.85 days.
The following example describes how a sequential circuit associated with an IC's DREG can be tested using 1149.1 TAP data register scan operations in a multiple IC environment shown in FIG. 7. The sequential circuit could be a subcircuit in the IC or the entire IC. As in the previous multiple IC test description, this type of testing would be done at a higher assembly level where the IC is combined with other ICs to form a system. The middle IC of FIG. 7, referred to as the target (T), in the group contains the DREG1 and sequential circuit of FIG. 6. There are “N” ICs between the target IC's TDI input and the test bus controller's TDO output and “M” ICs between the target ICs TDO and the test bus controller's TDI input.
During test the DISR, CISR, and DOSR of FIG. 6 operate as described in the test of the sequential circuitry in the single IC environment. The only difference between the multiple and single IC test environment is the length of the scan path between the test bus controller and the target IC.
Prior to testing, the test bus controller inputs test commands into the ICs of FIG. 7. ICs 1-N and ICs 1-M are loaded with a Bypass instruction to select their Bypass DREGs, and the target IC (T) is loaded with a test instruction that selects DREG1 and the sequential circuit for testing. In this configuration, the scan path length seen by the test bus controller is N bits (one bit for each IC 1-N), plus the target ICs DREG1 bits, plus M bits (one bit for each IC 1-M).
After loading the test commands the test bus controller inputs control to cause the TAP of each IC to execute multiple data register scan operations. Each data register scan operation repeats the steps of (1) capturing parallel data into the selected DREG of each IC in the scan path, (2) shifting data through the selected DREG of each IC in the scan path to output the captured data and input new test data, and (3) updating to parallel output the new test data from the selected DREG of each IC in the scan path. Step 1 and 3 (capturing and updating) require one TCK bus cycle each. Step 2 (shifting) requires a number of TCK bus cycles equal to the number of scan cells in the DISR (I), CISR (C), and DOSR (O), plus the number of scan cells in the Bypass DREG of ICs 1-N and 1-M of FIG. 7.
Once again, it is important to note that step 1 (parallel capture operation) causes the current data in the DREGs to be overwritten with the data captured. In the multiple IC environment this means that each time an 1149.1 data register scan operation is repeated, the new data to be shifted into the DISR and applied to the sequential circuit must traverse the entire length of Bypass DREGs of ICs 1-N between the test bus controller's TDO output and the target IC's TDI input. Likewise, the data captured in the DOSR of target IC must traverse the entire length of the Bypass DREGs of ICs 1-M between the target IC's TDO output and the test bus controller's TDI input. The Bypass DREGs of ICs 1-N and 1-M cannot be used to store or pipeline test data between the test bus controller and the target IC.
Equation 9 represents the number of TCK bus cycles required per data register scan operation, equation 5 represents the number of data register scan operations required to completely test the sequential circuit, and equation 10 represents the required test time.
                              #          ⁢                                          ⁢          of          ⁢                                          ⁢                      TCKs            /            scan                    ⁢                                          ⁢          operation                =                                            (              CaptureDR              )                        +                          (              ShiftDR              )                        +                          (              UpdateDR              )                                =                      (                          1              +              N              +              I              +              C              +              M              +              1                        )                                              Eq9        .                            Where: N=the # of bits before the target IC                    I=the # of DISR bits            C=the # of CISR bits            O=the # of DOSR bits            M=the # of bits after the target IC# of Scan Operations=2I×(1+2K)  Eq5Test Time=(Eq9)×(Eq5)×(1/TCKfreq)  Eq10                        
To establish a test time calculation benchmark for the multiple IC test environment using multiple 1149.1 TAP data register scan operations to test sequential circuits, assume that; N=500, C=1, I=16, K=3, O=16, M=500, and the TCK frequency=10 Mhz. The calculated test time to test the sequential circuit is:Test Time=(1+500+16+1+16+500+1)×(216×7)×( 1/10 Mhz)=47.48 seconds  Eq10
As in the single IC test environment, the complete testing of the IC in a multiple IC environment may require repeating the test on 100 other sequential circuits. In addition, the system may contain 1000 additional ICs of similar complexity as the one tested.
Testing 100 sequential circuits in an IC would take 4748 seconds or 79.1 minutes. Testing 1000 ICs of similar complexity would take 79,135 minutes or 1,319 hours or 54.95 days.
In view of the foregoing discussion, it is desirable to decrease the test access time to IC circuits via the 1149.1 test bus in both single and multiple IC testing environments.
The present invention includes a method and apparatus for emulating the operation of a data processing device using a serial bus and without cycling through multiple shift operations.